Physical Design Engineer

Overview We are seeking highly skilled Physical Design engineer 4 and above experince with strong hands-on expertise in Place & Route (PNR), Synthesis, and Signoff flows. The ideal candidate will have deep knowledge of timing closure, power analysis, and physical verification, along with exposure to low-power design methodologies (UPF). Key Responsibilities - Execute full-chip and block-level physical design including floorplanning, placement, CTS, routing, and optimization - Drive timing closure with a strong focus on Static Timing Analysis (STA) - Manage signoff activities including: - STA (Setup/Hold closure) - Physical Verification (DRC/LVS) - IR Drop and EM analysis - Perform logic synthesis ensuring timing, power, and area targets are met - Conduct and analyze VCLP (Voltage-aware checks) and LEC (Logical Equivalence Check) - Collaborate with RTL, DFT, and backend teams for design convergence - Debug and resolve timing, congestion, and power issues - Implement and verify low-power intent using UPF Mandatory Skills - Strong hands-on experience in PNR (Place & Route) – MUST - Expertise in Static Timing Analysis (STA) – HIGH PRIORITY - Experience in Synthesis and Signoff flows (STA, PV, IR/EM) - Knowledge of VCLP / LEC flows - Exposure to low-power design techniques and UPF

• Physical Design Lead (Full Chip)

  7Rays Semiconductors · Bengaluru, Karnataka, India