Senior Analog IC Design Engineer

Job Highlights - Senior‑level analog and mixed‑signal IC design role - High‑speed signal‑conditioning and interface products - SiGe BiCMOS and deep sub‑micron CMOS technologies - End‑to‑end silicon responsibility from architecture definition to silicon bring‑up - Clear growth path toward Principal / Technical Lead positions Principal Duties And Responsibilities - Act as a senior contributor in an analog/mixed‑signal IC development team, performing circuit design and verification for high‑speed products. - Define and own block‑level architecture, participate in system‑level architectural decisions, including performance, power and robustness trade‑offs. - Lead assigned designs from front‑end concept through schematic design, layout supervision, physical verification and tape‑out, aligning with overall product architecture. - Execute design verification, including transient, AC, noise, corner, Monte Carlo simulations and assess design margins. - Work closely with layout engineers to ensure proper matching, parasitic control and signal‑integrity‑aware implementation, providing clear technical direction. - Support post‑silicon bring‑up, validation and characterization, including lab measurements, silicon debug and correlation with simulation results. - Collaborate with product engineering, application engineering and test teams to support product qualification and production ramp. - Provide technical support for customer design‑in, debug and failure analysis as required. - Take ownership of design quality, technical risk and schedule commitments for assigned blocks or features. Knowledge, Skills And Abilities - M.S. in Electronic Engineering with 5+ years of relevant industry experience; PhD is a plus. - Proven experience in analog and mixed‑signal IC design with successful silicon tape‑outs. - Strong background in high‑speed analog circuit design, such as signal conditioning, equalization, clocking or data‑path circuits. - Experience with RF IC, SerDes or gigabit‑speed interfaces (e.g., USB, HDMI, DP, MIPI, PCIe) is highly desirable. - Proficient with Cadence and Synopsys design flows, including Spectre/HSPICE simulation. - Strong analytical, debugging and problem‑solving skills, including post‑silicon root‑cause analysis. - Self‑motivated, detail‑oriented and comfortable operating independently within a collaborative team environment. - Good written and verbal communication skills in English and Chinese; Mandarin is a plus. Interested parties, please send application letter and full resume with date of availability, current and expected salary. Please also quote the reference number on the application. Personal data provided will be treated in strict confidence and used for recruitment purpose only. Only shortlisted candidates will be notified. Applicants not invited for interview within eight weeks from the date of application may consider their applications unsuccessful.

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