Lead Verification Engineer (DSP)

About The Company Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads. Our infrastructure is designed around one principle: the signal should never be the bottleneck. General-purpose processors — CPUs, GPUs, DSPs — were not built for this class of problems. They approximate determinism. We built it in by architecture. Anthriq Silicon is our ground-up effort to build a new compute category. Key Responsibilities - Architect multi-agent UVM environments for a wide-issue VLIW pipeline (fetch, decode, hazard detection, execution units, in- flight credit model). - Build equivalence scoreboards: SystemVerilog RTL vs. C/C++ cycle-accurate ISS, integer and IEEE-754 FP. - Develop constrained-random assembly generators for 100% ISA and register-file coverage across a large custom opcode space. - Write SVA and drive formal property verification for arithmetic pipelines (fixed/float FMA, matrix multipliers, CORDIC, dividers). - Verify a compiler/hardware worst-case-timing contract (measured vs. claimed latency). - Execute and debug block-level SDF back-annotated GLS. Must-have Skills - 8+ years verifying processor cores (VLIW, SIMD, DSP, or custom RISC-V vector extensions). - Advanced SystemVerilog, UVM, SVA. - IEEE-754 floating-point AND fixed-point arithmetic-pipeline verification; matrix math, FFT/CORDIC. - Proven 100% functional-coverage closure on complex IP. Nice To Have - C/C++ reference modeling. - Formal tools / proof convergence. - WCET / timing-contract verification - Target EDA tools: Cadence Xcelium, JasperGold, vManager Skills: systemverilog,dsp,infrastructure,vliw,risc-v,ip,arithmetic,jaspergold,timing-contract verification,pipeline,signal,timing,cadence xcelium,c++,ieee-754

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